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Ordering number : ENN6498
CMOS IC
LC651432N/F/L, 651431N/F/L
Four-Bit CMOS Microcontrollers for Small-Scale Control Applications
Overview
The LC651431N/F/L and LC651432N/F/L are the smallscale control models in Sanyo's LC6500 Series of 4-bit microcontrollers and feature the same basic architecture and instruction set. These microcontrollers are appropriate for a wide range of applications, from applications that require only a limited number of circuits and controls and were previously implemented in standard logic to larger application such as audio equipment, including tape decks and disc players, office equipment, communication equipment, automotive equipment, and home appliances. Furthermore, since these products have equivalent basic functions (although there are differences in some functions and characteristics) and are pin compatible with the earlier LC6543N/F/L and LC6546N/F/L products, they can be used to replace those devices.
Features
* Fabricated in a CMOS process for low power operation (Standby mode can be controlled by CPU instructions.) * ROM/RAM LC651432N/F/L --ROM: 2 K x 8 bits, RAM: 128 x 4 bits LC651431N/F/L --ROM: 1 K x 8 bits, RAM: 64 x 4 bits * Instruction set: The 80-instruction set common to the whole LC6500 Series * Wide operating supply voltage range of 2.2 to 6.0 V (L versions) * Instruction cycle time of 0.92 s (F versions) * On-chip serial I/O function
* Highly flexible I/O ports Number of ports -- 7 ports (Up to 25 pins) All ports -- Can be used for either input or output -- Voltage handling capability (input and output): 15 V maximum (For open-drain specification ports) -- Output current: 20 mA maximum sink current (Capable of directly driving an LED.) I/O port options to match application requirements: -- Open-drain output and pull-up resistor specification: Can be specified for all ports in bit units. -- Output level at reset specification: Either a high or low level can be specified for ports C and D in 4-bit units each. * Interrupts Timer overflow vector interrupt (can also be tested by CPU instructions) INT pin or serial I/O full/empty vector interrupt (can also be tested by CPU instructions) * Stack levels: 4 levels (also used by interrupts) * Timers: 8-bit programmable timer with 4-bit prescaler * Clock oscillator options to match application requirements: Oscillator circuit option: -- Two-pin RC oscillator (N and L versions) Two-pin ceramic oscillator or single external clock input pin (N, F, and L versions) -- Divider circuit option: No divider, built-in divideby-three circuit, built-in divide-by-four circuit (N and L versions) * Continuous square-wave output with a period 64 times the cycle time.
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
40700RM (OT) No. 6498-1/39
LC651432N/F/L, 651431N/F/L
Package Dimensions
unit : mm 3196A-DIP30SD
[LC651432N/F/L, 651431N/F/L]
27.0
unit : mm 3191A-SSOP30
[LC651432N/F/L, 651431N/F/L]
30 16
30
16
10.16
8.6
5.6
0.95 3.0 3.95max (3.25)
0.25
1
9.75
15
1.5max
0.15
0.48
(1.04)
1.78
0.22
0.65
(0.33)
0.1 (1.3)
0.51min
SANYO: DIP30SD
SANYO: SSOP30
unit : mm 3216B-MFP30S
[LC651432N/F/L, 651431N/F/L]
30 16
15.2
0.4
1.0
(0.6)
0.1
(2.15)
SANYO: MFP30S
0.65
1
15
2.45max
0.15
10.5
7.9
0.5
1
15
No. 6498-2/39
7.6
LC651432N/F/L, 651431N/F/L Function Overview
Parameter ROM Memory RAM Instruction set Table reference Interrupts Timers On-chip functions Stack levels Standby function Number of ports Serial ports I/O voltage I/O ports Output current I/O circuit types Output level at reset Square-wave output Minimum cycle time Characteristics Supply voltage Supply current Oscillator element Divider circuit option Other features Package 2.77 s (VDD 3 V) 3 to 6 V 1 mA typ. RC oscillator (400 or 800 kHz typical) Ceramic oscillator (400 kHz, 800 kHz, 1 MHz, or 4 MHz) 1/1, 1/3, 1/4 LC651432N/1431N LC651432F/1431F 2048 x 8 bits (1432N/F/L) 1024 x 8 bits (1431N/F/L) 128 x 4 bits (1432N/F/L) 64 x 4 bits (1431N/F/L) 80 Provided One external, one internal 8-bit timer with 4-bit prescaler 4 HALT instruction based standby function Provided Up to 25 I/O pins I/O in 4-bit or 8-bit units 15 V max. 10 mA typ. 20 mA max. Open drain (n channel) or built-in pull-up resistor output can be specified in 1-bit units. High or low can be specified in port units (C and D ports only) Possible 0.92 s (VDD 3 V) 3 to 6 V 1.5 mA typ. Ceramic oscillator: 4 MHz 1/1 DIP30S-D, MFP30S, SSOP30 3.84 s (VDD 2.2 V) 2.2 to 6 V 1 mA typ. RC oscillator (400 kHz typical) Ceramic oscillator (400 kHz or 4 MHz) 1/1, 1/3, 1/4 LC651432L/1431L
Instructions
Oscillator
Note: Sanyo will be providing details on oscillator elements and oscillator circuit constants as recommended circuits are developed. Contact your Sanyo representative for more information.
No. 6498-3/39
LC651432N/F/L, 651431N/F/L Differences between the LC651432N/LC651431N and the LC6543N/LC6546N This table lists the points that require care when replacing the LC6543N/LC6546N with the LC651432N/LC651431N in completes end products.
Parameter Pdmax(1) : DIP Allowable power dissipation Pdmax(2) : MFP Pdmax(3) : SSOP I/O voltage (PIO) VIO(3) added LC651432N/1431N 310 mW 220 mW 160 mW -0.3 to VDD + 0.3 VIH(1) to VIH(7) (Associated with the I/O voltage (PI0) changes mentioned above.) IIH(1) to IIH(3) (Associated with the I/O voltage (PI0) changes mentioned above.) Oscillator frequency precision: 2% Recommended oscillator circuit constants (under evaluation) 800 kHz typical (VDD = 3 to 6 V) Circuit constant changes: Rext = 6.8 k 1% Sample-to-sample frequency variation: 595 to 1274 kHz 400 kHz typical (VDD = 3 to 6 V) Sample-to-sample frequency variation: 284 to 790 kHz Current drain Serial clock input clock cycle time Package IDD tCKCY(1)[SCK] 1 mA typ. min. 2.0 s DIP30S-D, MFP30S, SSOP30 added LC6543N/46N 250 mW 150 mW (This package not available.) -0.3 to +15 V (When open-drain output is used.) -0.3 to VDD + 0.3 (When a pull-up resistor is used.) VIH(1) to VIH(6)
High-level input voltage
VIH(n)
High-level input current
IIH(n)
IIH(1) to IIH(2)
fCFOSC [OSC1, OSC2] Oscillator characteristics Ceramic oscillator Oscillator frequency 2-pin RC oscillator Oscillator frequency
Oscillator frequency precision: 4% 850 kHz typical (VDD = 4 to 6 V) Circuit constant changes: Rext = 4.7 k 1% Sample-to-sample frequency variation: 619 to 1144 kHz 400 kHz typical (VDD = 3 to 6 V) Sample-to-sample frequency variation: 305 to 546 kHz 2 mA typ. min 3.0 s DIP30S-D, MFP30S
fMOSC [OSC1, OSC2]
Differences between the LC651432F/LC651431F and the LC6543F/LC6546F This table lists the points that require care when replacing the LC6543F/LC6546F with the LC651432F/LC651431F in completes end products.
Parameter Pdmax(1) : DIP Allowable power dissipation Pdmax(2) : MFP Pdmax(3) : SSOP Operating supply voltage I/O voltage (PI0) VDD VIO(3) added LC651432F/1431F 310 mW 220 mW 160 mW 3 to 6 V -0.3 to VDD + 0.3 VIH(1) to VIH(7) (Associated with the I/O voltage (PI0) changes mentioned above.) IIH(1) to IIH(3) (Associated with the I/O voltage (PI0) changes mentioned above.) IIH(1) to IIH(3) Specifications when VDD = 4 to 6 V Specifications added for VDD = 3 to 6 V Oscillator frequency precision: 2% 1.5 mA typ. min. 2.0 s DIP30S-D, MFP30S, SSOP30 added LC6543F/46F 250 mW 150 mW (This package not available.) 4.5 to 6 V -0.3 to +15 V (When open-drain output is used.) -0.3 to VDD + 0.3 (When a pull-up resistor is used.) VIH(1) to VIH(6)
High-level input voltage
VIH(n)
High-level input current
IIH(n)
IIH(1) to IIH(2)
Low-level input voltage Oscillator characteristics Ceramic oscillator Oscillator frequency Current drain Serial clock input clock cycle time Package
VIL(n)
Specifications when VDD = 4 to 6 V
fCFOSC [OSC1, OSC2] IDD tCKCY(1)[SCK]
Oscillator frequency precision: 4% 2.5 mA typ. min 3.0 s DIP30S-D, MFP30S
No. 6498-4/39
LC651432N/F/L, 651431N/F/L Differences between the LC651432L/LC651431L and the LC6543L/LC6546L This table lists the points that require care when replacing the LC6543L/LC6546L with the LC651432L/LC651431L in completes end products.
Parameter Pdmax(1) : DIP Allowable power dissipation Pdmax(2) : MFP Pdmax(3) : SSOP I/O voltage (PI0) VIO(3) added LC651432L/1431L 310 mW 220 mW 160 mW -0.3 to VDD + 0.3 VIH(1) to VIH(7) (Associated with the I/O voltage (PI0) changes mentioned above.) IIH(1) to IIH(3) (Associated with the I/O voltage (PI0) changes mentioned above.) Oscillator frequency precision: 2% Recommended oscillator circuit constants (under evaluation) 400 kHz typical (VDD = 2.2 to 6 V) Circuit constant changes: Rext = 15 k 1% Sample-to-sample frequency variation: 200 to 790 kHz 1 mA typ. DIP30S-D, MFP30S, SSOP30 added LC6543L/46L 250 mW 150 mW (This package not available.) -0.3 to +15 V (When open-drain output is used.) -0.3 to VDD + 0.3 (When a pull-up resistor is used.) VIH(1) to VIH(6)
High-level input voltage
VIH(n)
High-level input current
IIH(n)
IIH(1) to IIH(2)
Oscillator characteristics Ceramic oscillator Oscillator frequency 2-pin RC oscillator Oscillator frequency Current drain Package
fCFOSC [OSC1, OSC2]
Oscillator frequency precision: 4% 400 kHz typical (VDD = 2.2 to 6 V) Circuit constant changes: Rext = 12 k 1% Sample-to-sample frequency variation: 284 to 546 kHz 2 mA typ. DIP30S-D, MFP30S
fMOSC [OSC1, OSC2] IDD
Caution: Always test the end product thoroughly after changing the microcontroller used.
Pin Assignment The same pin assignment is used for the DIP, MFP, and SSOP packages.
LC651432N/F/L LC651431N/F/L
PG3 10 PA0 11 PA1 12 PA2 13 PA3 14 PI0/OSC2 15
PE3 1
VDD 2
PF0/SI 3
PF1/SO 4
PF2/SCK 5
PF3/INT 6
PG0 7
PG1 8
PG2 9
16 OSC1
17 TEST
19 RES
18 VSS
27 PD3
26 PD2
25 PD1
24 PD0
23 PC3
22 PC2
21 PC1
20 PC0
30 PE2
29 PE1
28 PE0
No. 6498-5/39
LC651432N/F/L, 651431N/F/L Pin Nomenclature OSC1, OSC2: Connections for capacitor and resistor oscillator components or a ceramic oscillator element. PG0 to 3: Shared-function I/O port G0 to 3 PI0: Shared-function I/O port IO RES: Reset TEST: Test PA0 to 3: Shared-function I/O port A0 to 3 INT: Interrupt request PC0 to 3: Shared-function I/O port C0 to 3 SI: Serial input PD0 to 3: Shared-function I/O port D0 to 3 SO: Serial output PE0 to 3: Shared-function I/O port E0 to 3 SCK: Serial clock input or output pin PF0 to 3: Shared-function I/O port F0 to 3 Notes: 1. The SI, SO, SCK, and INT pins are shared-function pins also used as PF0 to 3. 2. OSC2 and PIO are a single pin set exclusively to one or the other function as a user option. System Block Diagram
LC651432N/F/L, LC651431N/F/L
PA0 to 3
Port A I/O buffer
RAM F WR DP
PC STACK 1 STACK 2 STACK 3 STACK 4
ROM
PC0 to 3
Port C
IR
I.DEC
PD0 to 3
Port D
PE0 to 3
Port E
System bus
PF0 to 3
Port F
E
AC ALU
PF1/SO 4/8 bits
Serial shift register Lower digit Serial shift register Higher
STS CF ZF EXTF TMF CSF ZSF
TM INT
CTL
Shared with port F
Serial mode register
Serial mode register
OSC
OSC1 OSC2* RES TEST VDD VSS
I/O bus
4 bits
Port G
Port I
PF0/SI PF2/SCK PF3/INT
4/8 bits PG0-3 PI0 *
Note: * OSC2 and PIO are a single pin set exclusively to one or the other function as a user option.
RAM: F: WR: AC: ALU: DP: E: CTL: OSC: TM: STS:
Data memory Flags Working register Accumulator Arithmetic and logic unit Data pointer E register Control register Oscillator circuit Timer Status register
ROM: PC: INT: IR: I.DEC: CF, CSF: ZF, ZSF: EXTF: TMF:
Program memory Program counter Interrupt control Instruction register Instruction decoder Carry flag, carry save flag Zero flag, zero save flag External interrupt request flag Internal interrupt request flag
No. 6498-6/39
LC651432N/F/L, 651431N/F/L Development Support The following are available to support the development of LC651431 and LC651432 applications. * User's manual "LC6543/46 User's Manual" No. E71 * Development tool manual See the "EVA86000 Development Tool Manual for 4-Bit Microcontrollers." * Software manual "LC65/66 Series Software Manual" * Development tools Program development: EVA86000 System Program evaluation: LC65E43 on-chip EPROM microcontroller
Pins Functions
Count 1 1 1 Pin VDD VSS OSC1 I/O -- -- Input * Connection for the external system clock RC or ceramic oscillator element * When a single pin is used for external clock input, the PI0/OSC2 pin is used as the PI0 I/O port. * When a 2-pin RC oscillator or a 2-pin ceramic oscillator is used, the PI0/OSC2 pin is used as the OSC2 oscillator pin. 1. 2. 3. 4. Single-pin external clock input 2-pin RC oscillator 2-pin ceramic oscillator Divider circuit option * No divider * Divide-by-three circuit * Divide-by-four circuit -- -- Power supply Function -- Options -- Reset state Handling when unused --
4
PA0 to PA3
I/O
* I/O port A0 to 3 1. Open-drain output * High-level Input in 4-bit units (IP instruction) 2. Built-in pull-up resistor output (with Output in 4-bit units (OP instruction) Options 1 and 2 may be specified the output nTest in single-bit units (BP and BNP instructions) in bit units. channel Set/reset in single-bit units (SPB and RPB transistor off) instructions) * PA3 (Any one of PA0 to 3 can be selected) is used for standby mode control. * Applications must assure that key bounce or similar noise does not occur on PA3 (or PA0 to 3) during a HALT instruction execution cycle. * I/O port C0 to 3 Provides the same functions as PA0 to 3. (See note.) * The output level at reset can be specified to be either high or low. Note: This port does not have the standby mode control function. * I/O port D0 to 3 Provides the same functions as PC0 to 3. 1. Open-drain output 2. Built-in pull-up resistor 3. High-level output at reset 4. Low-level output at reset * Options 1 and 2 may be specified in bit units. * Options 3 and 4 are specified in a single 4-bit group The same as those for PC0 to 3. * High-level output * Low-level output (Specified as a user option.)
The open-drain output option must be selected and the pin connected to VSS.
4
PC0 to PC3
I/O
The same as that for PC0 to 3
4
PD0 to PD3
I/O
The same as The same as those for PC0 to 3. those for PC0 to 3.
Continued on next page.
No. 6498-7/39
LC651432N/F/L, 651431N/F/L
Continued from preceding page.
Count 4 Pin PE0 to PE3 I/O I/O Function * I/O port E0 to 3 Input in 4-bit units (IP instruction) Output in 4-bit units (OP instruction) Set/reset in single-bit units (SPB and RPB instructions) Test in single-bit units (BP and BNP instructions) * PE0 also has a continuous pulse (64Tcyc) output function. * I/O port F0 to 3 Functions and options identical to PE0 to 3. (See note.) * PF0 to 3 have shared functions as the serial interface pins and the INT input. Either function can be selected under program control. SI ... Serial input port SO ... Serial output port SCK ... Serial clock input or output INT ... Interrupt request input Serial input/output is switched between 4-bit and 8-bit units under program control. Note: This port does not have a continuous pulse output function. * I/O port G0 to 3 Functions and options identical to PE0 to 3. (See note.) Note: This port does not have a continuous pulse output function. Options Reset state Handling when unused The same as that for PA0 to 3.
1. Open-drain output * High-level 2. Built-in pull-up resistor output (with Options 1 and 2 may be specified the output nin bit units. channel transistor off)
4
PF0/SI PF1/SO PF2/SCK PF3/INT
I/O
The same as those for PE0 to 3.
The same as The same as that for PE0 to 3. that for The serial port PA0 to 3. is disabled and INT is the interrupt source.
4
PG0 to PG3
I/O
The same as those for PE0 to 3.
The same as those for PE0 to 3.
The same as that for PA0 to 3.
1
PI0/OSC2
I/O * I/O port IO Output Functions and options identical to PG0 to 3. * However, consists of a single bit. * When a 2-pins oscillator is used, this pin functions as the OSC2 pin, and the I/O port function is not available. Input * System reset input * Connect an external capacitor to implement a power-on reset. * The reset start operation requires that a low level be held for at least 4 clock cycles. * IC test pin This pin must be connected to VSS during normal operation.
The same as those for PG0 to 3.
The same as those for PG0 to 3.
The same as that for PA0 to 3.
1
RES
--
--
--
1
TEST
Input
--
--
This pin must be connected to VSS.
No. 6498-8/39
LC651432N/F/L, 651431N/F/L Oscillator Circuit Options
Option Circuit Conditions and notes
External clock
OSC1
The PI0/OSC2 pin is used as the PI0 pin.
Cext
Two-pin RC oscillator
OSC1
The PI0/OSC2 pin is used as the OSC2 pin and the port function is unavailable.
PI0/OSC Rext C1 OSC1
The PI0/OSC2 pin is used as the OSC2 pin and the port function is unavailable.
Ceramic oscillator
Ceramic oscillator element C2 R
PI0/OSC
Divider Circuit Options
Option Circuit Conditions and notes * Applicable to all three oscillator options. * The oscillator frequency or the external clock must not exceed 1444 kHz. (LC651431N and LC651432N) * The oscillator frequency or the external clock must not exceed 4330 kHz. (LC651431F and LC651432F) * The oscillator frequency or the external clock must not exceed 1040 kHz. (LC651431L and LC651432L)
Oscillator circuit
No divider circuit (1/1)
fOSC
Oscillator circuit
Timing generator
Divide-by-three circuit (1/3)
fOSC
Timing generator
fOSC 3 Divide-by-three circuit
* Only applicable to the external clock and the ceramic oscillator option. * The oscillator frequency or the external clock must not exceed 4330 kHz.
Oscillator circuit
Divide-by-four circuit (1/4)
fOSC
Divide-by-four circuit
Timing generator
fOSC 4
* Only applicable to the external clock and the ceramic oscillator option. * The oscillator frequency or the external clock must not exceed 4330 kHz.
Caution: The following table summarizes the oscillator and divider option combinations. Use care when selecting these options.
No. 6498-9/39
LC651432N/F/L, 651431N/F/L Oscillator Divider Options for the LC651431N/LC651432N, LC651431F/LC651432F, and LC651431L/LC651432L LC651432N, LC651431N
Oscillator type Ceramic oscillator Frequency 400 kHz 800 kHz Divider option (cycle time) 1/1 (10 s) 1/1 (5 s) 1/3 (15 s) 1/4 (20 s) 1 MHz 1/1 (4 s) 1/3 (12 s) 1/4 (16 s) 4 MHz 1/3 (3 s) 1/4 (4 s) Single-pin external clock input 200 to 1444 kHz 600 to 4330 kHz 800 to 4330 kHz External clock provided by a 2-pin RC oscillator circuit 2-pin RC oscillator As above Using the no-divider (1/1) option and the 3 to 6 V recommended circuit constants. If the use of circuit values other than the recommended values is unavoidable, the frequencies, divider options, and VDD ranges specified for the single-pin external clock input option must be strictly observed. The IC cannot be driven by an external clock with this option. If external clock drive is required, select either the external clock option or the 2-pin RC oscillator option 1/1 (20 to 2.77 s) 1/3 (20 to 2.77 s) 1/4 (20 to 3.70 s) VDD range 3 to 6 V 3 to 6 V 3 to 6 V 3 to 6 V 3 to 6 V 3 to 6 V 3 to 6 V 3 to 6 V 3 to 6 V 3 to 6 V 3 to 6 V 3 to 6 V The no-divider (1/1) option cannot be used. Notes The divide-by-three and divide-by-four circuits cannot be used.
External clock used with the ceramic oscillator option
LC651432F, LC651431F
Oscillator type Ceramic oscillator Single-pin external clock input External clock used with the ceramic oscillator circuit Frequency 4 MHz 200 to 4330 kHz Divider option (cycle time) 1/1 (1 s) 1/1 (20 to 0.92 s) VDD range 3 to 6 V 3 to 6 V Notes
The IC cannot be driven by an external clock with this option. If external clock drive is required, select the external clock option.
LC651432L, LC651431L
Oscillator type Ceramic oscillator Frequency 400 kHz 4 MHz Single-pin external clock input 200 to 1040 kHz 600 to 3120 kHz 800 to 4160 kHz External clock provided by a 2-pin RC oscillator circuit 2-pin RC oscillator As above Using the no-divider (1/1) option and the 2.2 to 6 V recommended circuit constants. If the use of circuit values other than the recommended values is unavoidable, the frequencies, divider options, and VDD ranges specified for the single-pin external clock input option must be strictly observed. The IC cannot be driven by an external clock with this option. If external clock drive is required, select either the external clock option or the 2-pin RC oscillator option Divider option (cycle time) 1/1 (10 s) 1/4 (4 s) 1/1 (20 to 3.84 s) 1/3 (20 to 3.84 s) 1/4 (20 to 3.84 s) VDD range 2.2 to 6 V 2.2 to 6 V 2.2 to 6 V 2.2 to 6 V 2.2 to 6 V Notes The divide-by-three and divide-by-four circuits cannot be used. The no-divider (1/1) and divide-by-three option cannot be used.
External clock used with the ceramic oscillator option
No. 6498-10/39
LC651432N/F/L, 651431N/F/L Port C and D Output Level at Reset Option One of the following two options for the output level at reset may be chosen for the I/O ports C and D in 4-bit group units.
Option High-level output at reset Low-level output at reset Conditions and notes Ports C and D in 4-bit units Ports C and D in 4-bit units
Port Output Circuit Type Option One of the following two options for the circuit type can be selected for the I/O ports in bit units.
Option Circuit Applicable ports
Open-drain output
* Not applicable to the PI0/OSC2 pin if either the 2-pin RC oscillator or the ceramic oscillator is selected as the oscillator circuit.
Built-in pull-up resistor output
No. 6498-11/39
LC651432N/F/L, 651431N/F/L
Specifications LC651432N, 651431N
Absolute Maximum Ratings at Ta = 25C, VSS = 0 V
Parameter Maximum supply voltage Output voltage Symbol VDD max VO VI(1) VI(2) VIO(1) I/O voltage VIO(2) VIO(3) Peak output current IOP IOA IOA(1) Per single pin, the average over a 100 ms period The total current for PC0 to 3, PD0 to 3, and PE0 to 3*2 The total current for PF0 to 3, PG0 to 3, PA0 to 3, and PI0*2 Conditions VDD OSC2 OSC1 *1 TEST, RES Ports with open-drain specifications Ports with pull-up resistor specifications PI0 I/O ports I/O ports PC0 to 3 PD0 to 3 PE0 to 3 PF0 to 3, PI0 PG0 to 3 PA0 to 3 Applicable pins Ratings -0.3 to +7.0 Voltages up to the voltage generated are allowed. -0.3 to VDD +0.3 -0.3 to VDD +0.3 -0.3 to +15 -0.3 to VDD +0.3 -0.3 to VDD +0.3 -2 to +20 -2 to +20 Unit V V V V V V V mA mA mA
Input voltage
Average output current
-15 to +100
IOA(2)
-15 to +100 310 220 160 -40 to +85 -55 to 125
mA mW mW mW C C
Pd max(1) Ta = -40 to +85C (DIP package) Allowable power dissipation Pd max(2) Ta = -40 to +85C (MFP package) Pd max(3) Ta = -40 to +85C (SSOP package) Operating temperature Storage temperature Topr Tstg
Allowable Operating Ranges at Ta = -40 to +85C, VSS = 0 V, VDD = 3.0 to 6.0 V (unless otherwise specified)
Parameter Operating supply voltage Standby supply voltage Symbol VDD VST VIH(1) VIH(2) VIH(3) High-level input voltage VIH(4) VIH(5) VIH(6) VIH(7) RAM and register contents retained. *3 With the n-channel output transistors off With the n-channel output transistors off With the n-channel output transistors off With the n-channel output transistors off With the n-channel output transistors off VDD = 1.8 to 6 V External clock specifications Conditions VDD VDD Ports with open-drain specifications (except for I0) Ports with pull-up resistor specifications (except for I0) Port I0 The INT, SCK, and SI pins with open-drain specifications The INT, SCK, and SI pins with pull-up resistor specifications RES OSC1 Applicable pins Ratings min 3.0 1.8 0.7 VDD 0.7 VDD 0.7 VDD 0.8 VDD 0.8 VDD 0.8 VDD 0.8 VDD typ max 6.0 6.0 13.5 VDD VDD 13.5 Unit V V V V V V
VDD VDD VDD
V V V
Continued on next page.
No. 6498-12/39
LC651432N/F/L, 651431N/F/L
Continued from preceding page.
Parameter Symbol Conditions With the n-channel output transistors off VDD = 4 to 6 V With the n-channel output transistors off 3 to 6 V With the n-channel output transistors off VDD = 4 to 6 V With the n-channel output transistors off 3 to 6 V External clock specifications VDD = 4 to 6 V External clock specifications 3 to 6 V VDD = 4 to 6 V 3 to 6 V VDD = 4 to 6 V 3 to 6 V A clock frequency of up to 4.33 MHz may be used when either the divide-by-three circuit or the divide-by-four circuit is used. See figure 1. The divide-by-three circuit or the divide-by-four circuit textH, textL must be used if the clock frequency exceeds 1.444 textR, textF MHz. text OSC1 OSC1 OSC1 200 69 50 4330 kHz ns ns Applicable pins Ratings min VSS typ max 0.3 VDD Unit
VIL(1)
Port
V
VIL(2)
Port
VSS
0.25 VDD
V
VIL(3)
INT, SCK, SI
VSS
0.25 VDD
V
VIL(4) Low-level input voltage VIL(5) VIL(6) VIL(7) VIL(8) VIL(9) VIL(10)
INT, SCK, SI
VSS
0.2 VDD
V
OSC1 OSC1 TEST TEST RES RES
VSS VSS VSS VSS VSS VSS
0.25 VDD 0.2 VDD 0.3 VDD 0.25 VDD 0.25 VDD 0.2 VDD
V V V V V V
Operating frequency (cycle time)
fop (Tcyc)
200 (20)
1444 (2.77)
kHz (s)
External clock conditions Frequency Pulse width Rise and fall time Recommended oscillator circuit constants Two-pin RC oscillator Cext Rext Cext Rext Ceramic oscillator*4
See figure 2.
OSC1, OSC2
220 5% 12 1%
pF k pF k
See figure 2. See figure 3.
OSC1, OSC2
220 5% 6.8 1% See table 1.
No. 6498-13/39
LC651432N/F/L, 651431N/F/L Electrical Characteristics at Ta = -40 to +85C, VSS = 0 V, VDD = 3.0 to 6.0 V (unless otherwise specified)
Parameter Symbol Conditions * With the output n-channel transistors off (Including the n-channel transistor off leakage current.) * VIN = 13.5 V * With the output n-channel transistors off (Including the n-channel transistor off leakage current.) * VIN = VDD * External clock mode * VIN = VDD * With the output n-channel transistors off * VIN = VSS * With the output n-channel transistors off * VIN = VSS VIN = VSS * External clock mode * VIN = VSS * IOH = -50 A * VDD =4.0 to 6.0 V * IOH = -10 A * IOL = 10 mA * VDD = 4.0 to 6.0 V IOL = 1 mA, when IOL for all ports is less than or equal to 1 mA. Applicable pins Open-drain specification ports (except I0) 5.0 A Ratings min typ max Unit
IIH(1)
High-level input current IIH(2)
The I0 port with open-drain specifications 1.0 A
IIH(3) IIL(1)
OSC1
1.0
A
Open-drain specification ports Built-in pull-up resistor specification ports RES OSC1 Built-in pull-up resistor specification ports Built-in pull-up resistor specification ports Ports
-1.0
A
Low-level input current
IIL(2) IIL(3) IIL(4) VOH(1)
-1.3 -45 -1.0 VDD - 1.2 VDD - 0.5
-0.35 -10
mA A A V V
High-level output voltage VOH(2) VOL(1) Low-level output voltage VOL(2) Schmitt characteristics
1.5
V
Ports
0.5
V
Hysteresis voltage
VHIS RES, INT, SCK, SI, and OSC1 with Schmitt trigger specifications*5
0.1 VDD
V
High-level threshold voltage
VtH
0.4 VDD
0.8 VDD
V
Low-level threshold voltage
VtL
0.2 VDD
0.6 VDD
V
Current drain*6 Two-pin RC oscillator IDDOP(1) * While operating, with the output n-channel transistors off * Port voltage = VDD * Figure 2, fosc = 800 kHz (typical) See figure 2. fosc = 400 kHz (typical) * Figure 3, 4 MHz, divideby-three circuit used. * Figure 3, 4 MHz, divideby-four circuit used. See figure 3. 400 kHz See figure 3. 800 kHz
VDD
1
3
mA
Ceramic oscillator
IDDOP(2) IDDOP(3)
VDD VDD VDD VDD VDD
0.8 1 1 1 1
2.5 3 3 2.5 3
mA mA mA mA mA
External clock Standby mode
IDDOP(4) IDDOP(5) IDDOP(6)
IDDOP(7)
* 200 to 1444 kHz, no divider * 600 to 4330 kHz, divideby-three circuit used VDD * 800 to 4330 kHz, divideby-four circuit used Output n-channel transistors off, VDD = 6 V Port voltage = VDD, VDD = 3 V VDD VDD
1
4
mA
0.05 0.025
10 5
A A
IDDst
Continued on next page.
No. 6498-14/39
LC651432N/F/L, 651431N/F/L
Continued from preceding page.
Parameter Oscillator characteristics Ceramic oscillator Oscillator frequency fCFOSC*7 * * * * Figure 3, fo = 400 kHz Figure 3, fo = 800 kHz Figure 3, fo = 1 MHz Figure 3, fo = 4 MHz, divide-by-three or divideby-four circuit used. OSC1, OSC2 OSC1, OSC2 OSC1, OSC2 OSC1, OSC2 392 784 980 3920 400 800 1000 4000 408 816 1020 4080 kHz kHz kHz kHz Symbol Conditions Applicable pins Ratings min typ max Unit
Oscillator stabilization time*8 tCFS
* Figure 4, fo = 400 kHz * Figure 4, fo = 800 kHz, 1 MHz, or 4 MHz, divideby-three or divide-by-four circuit used. * Figure 2, Cext = 220 pF 5% OSC1, OSC2 * Figure 2, Rext = 6.8 k 1% * Figure 2, Cext = 220 pF 5% OSC1, OSC2 * Figure 2, Rext = 12 k 1% * Output n-channel transistors off * VIN = VSS, VDD = 5 V * VIN = VSS, VDD = 5 V Ports with built-in pull-up resistor specifications RES 595 284 800 400
10 10
ms ms
Two-pin RC oscillator Oscillator frequency
1274 790
kHz kHz
fMOSC
Built-in pull-up resistor I/O ports RES
RPP Ru
8 200
14 500 See figure 5.
30 800
k k
External reset characteristics Reset time Pin capacitance Serial clock Input clock cycle time Output clock cycle time Input clock low-level pulse width Output clock low-level pulse width Input clock high-level pulse width Output clock high-level pulse width Serial input Data setup time Data hold time Serial output Output delay time
tRST Cp * f = 1 MHz * With all pins except the pin being tested at VIN = VSS. See figure 6. See figure 6. See figure 6. SCK SCK SCK SCK SCK SCK 1.0 1.0 2.0
10
pF
tCKCY(1) tCKCY(2) tCKL(1)
s 64 x TCYC*9 s s 32 x TCYC s s 32 x TCYC s
tCKL(2) tCKH(1) tCKH(2)
See figure 6. See figure 6. See figure 6.
tICK tCKI tCKO
Stipulated with respect to the SCK rising edge. See figure 6.
SI SI
0.5 0.5
s s
* Stipulated with respect to the SCK falling edge. * With external 1 k resistors and 50 pF capacitors on the n-channel open-drain outputs only. * See figure 6.
SO
0.5
s
Continued on next page.
No. 6498-15/39
LC651432N/F/L, 651431N/F/L
Continued from preceding page.
Parameter Pulse output Period High-level pulse width tPCY tPH Symbol Conditions Applicable pins Ratings min typ 64 x TCYC 32 x TCYC 10% 32 x TCYC 10% max Unit
* See figure 7 * TCYC = 4 x
PE0
s s
Low-level pulse width
tPL
PE0 * With external 1 k resistors and external 50 pF capacitors on the nchannel open-drain outputs PE0 only.
s
Notes: 1. Voltages up to the generated oscillation amplitude are allowed with internal drive using the oscillator circuit of figure 3 and the recommended circuit constants. 2. The average over a 100 ms period. 3. Applications must hold the operating supply voltage VDD level from the point a HALT instruction is executed until the IC enters the standby state. Also, switch bounce and similar noise must not appear on PA3 (or PA0 to 3) during the HALT instruction execution cycle. 4. The recommended circuit constants for which stable oscillation has been verified with the manufacturer of the oscillator element using the Sanyo specified oscillator characteristics evaluation board. 5. The OSC1 pin has Schmitt trigger characteristics when either 2-pin RC oscillator or external clock input is specified as the oscillator option. 6. The result of measurement when the recommended external circuit constants are used with the Sanyo characteristics evaluation board. The current due to the IC output transistors and pull-up resistor transistors is not included. 7. Indicates the frequency when fCFOSC is due to the use of the recommended circuit constants in table 1. 8. Indicates the required time for oscillation to stabilize starting from the point when VDD first exceeds the lower limit of the operating supply voltage range. (See figure 4.) 9. TCYC = 4 x
No. 6498-16/39
LC651432N/F/L, 651431N/F/L
OSC1
(OSC2)
External clock
Open
VDD 0.8 VDD
0.2 VDD VSS
text
text
text text
text
Figure 1 External Clock Input Waveform
OSC1
OSC2
OSC1
OSC2
R Rext Cext C1 Ceramic oscillator element C2
Figure 2 Two-Pin RC Oscillator Circuit
Figure 3 Ceramic Oscillator Circuit
No. 6498-17/39
LC651432N/F/L, 651431N/F/L
VDD
Lower limit of the operating VDD range 0V
OSC
Oscillator stabilization time tCFS
Stable oscillation
Figure 4 Oscillator Stabilization Time
Table 1 Ceramic Oscillator Recommended Circuit Constants
4 MHz (Murata Mfg. Co., Ltd.) CSA4.00MG CST4.00MGW (Built-in capacitor) 4 MHz (Kyocera Corporation) KBR4.0MSB KBR4.0MKC (Built-in capacitor) 1 MHz (Murata Mfg. Co., Ltd.) CSB1000J C1 C2 R C1 C2 R C1 C2 R 800 kHz (Murata Mfg. Co., Ltd.) CSB800J C1 C2 R 400 kHz (Murata Mfg. Co., Ltd.) CSB400P C1 C2 R 33 pF 10% 33 pF 10% 0 33 pF 10% 33 pF 10% 0 100 pF 10% 100 pF 10% 2.2 k 100 pF 10% 100 pF 10% 2.2 k 220 pF 10% 220 pF 10% 2.2 k Note: When the power supply rise time is effectively zero, the reset time for a CRES of 0.1 F will be between 10 and 100 ms. If the power supply rise time is relatively long, increase the value of CRES so that the reset time is over 10 ms.
RES CRES ( = 0.1 F)
Figure 5 Reset Circuit
No. 6498-18/39
LC651432N/F/L, 651431N/F/L
tCKCY 0.8 VDD tCKL SCK tICK SI tCKO SO Output data 50 pF tCKI 1 k tCKH 0.2 VDD
VDD
Input data Load circuit
Figure 6 Serial I/O Timing
tPCY tPH 0.7 VDD tPL The load conditions are the same as those in figure 6. 0.25 VDD
Figure 7 Port PE0 Pulse Output Timing
No. 6498-19/39
LC651432N/F/L, 651431N/F/L LC651431N and LC651432N RC Oscillator Characteristics Figure 8 shows the LC651431N and LC651432N RC oscillator characteristics. However, the LC651431N and LC651432N have the following RC oscillator frequency sample-to-sample variations. 1) VDD = 3.0 to 6.0 V, Ta = -40 to 85C When the external circuit constants are: Cext = 220 pF, and Rext = 12 k, the frequency range will be: 284 kHz fMOSC 790 kHz 2) VDD = 3.0 to 6.0 V, Ta = -40 to 85C When the external circuit constants are: Cext = 220 pF, and Rext = 6.8 k, the frequency range will be: 595 kHz fMOSC 1274 kHz Note that only the above circuit constants are guaranteed. If using other values for these constants is unavoidable, use values in the following ranges. Cext = 150 to 390 pF Rext = 3 to 20 k (See figure 8.)
Notes: 10. The oscillator frequency must be in the range 350 to 750 kHz when VDD = 5.0 V and Ta = 25C. 11. Applications must assure adequate margins so that oscillator frequency falls in the operating clock frequency range (in the oscillator divider option table) for the ranges VDD = 3.0 to 6.0 V and Ta = -40 to 85C.
f 1.5
MOSC-Rext
C = 150p
These characteristics curves are for reference purposes only. These characteristics are not guaranteed.
[kHz]
1000 9 8 7 6 5 4 3
C = 270p
f
MOSC
C = 390p
2
VDD = 5 (V) Ta = 25C 1000 3 4 5 1 Rext [k] 2 3 4 5 10
Figure 8 RC Oscillator Frequency Data (representative values)
No. 6498-20/39
LC651432N/F/L, 651431N/F/L
LC651432F, 651431F
Absolute Maximum Ratings at Ta = 25C, VSS = 0 V
Parameter Maximum supply voltage Output voltage Symbol VDD max VO VI(1) VI(2) VIO(1) I/O voltage VIO(2) VIO(3) Peak output current IOP IOA IOA(1) Per single pin, the average over a 100 ms period The total current for PC0 to 3, PD0 to 3, and PE0 to 3*2 The total current for PF0 to 3, PG0 to 3, PA0 to 3, and PI0*2 Conditions VDD OSC2 OSC1 *1 TEST, RES Ports with open-drain specifications Ports with pull-up resistor specifications PI0 I/O ports I/O ports PC0 to 3 PD0 to 3 PE0 to 3 PF0 to 3, PI0 PG0 to 3 PA0 to 3 Applicable pins Ratings -0.3 to +7.0 Voltages up to the voltage generated are allowed. -0.3 to VDD +0.3 -0.3 to VDD +0.3 -0.3 to +15 -0.3 to VDD +0.3 -0.3 to VDD +0.3 -2 to +20 -2 to +20 Unit V V V V V V V mA mA mA
Input voltage
Average output current
-15 to +100
IOA(2)
-15 to +100 310 220 160 -40 to +85 -55 to 125
mA mW mW mW C C
Pd max(1) Ta = -40 to +85C (DIP package) Allowable power dissipation Pd max(2) Ta = -40 to +85C (MFP package) Pd max(3) Ta = -40 to +85C (SSOP package) Operating temperature Storage temperature Topr Tstg
Allowable Operating Ranges at Ta = -40 to +85C, VSS = 0 V, VDD = 3.0 to 6.0 V (unless otherwise specified)
Parameter Operating supply voltage Standby supply voltage Symbol VDD VST VIH(1) VIH(2) VIH(3) High-level input voltage VIH(4) VIH(5) VIH(6) VIH(7) RAM and register contents retained.*3 With the n-channel output transistors off With the n-channel output transistors off With the n-channel output transistors off With the n-channel output transistors off With the n-channel output transistors off VDD = 1.8 to 6 V External clock specifications Conditions VDD VDD Ports with open-drain specifications (except for I0) Ports with pull-up resistor specifications (except for I0) Port I0 The INT, SCK, and SI pins with open-drain specifications The INT, SCK, and SI pins with pull-up resistor specifications RES OSC1 Applicable pins Ratings min 3.0 1.8 0.7 VDD 0.7 VDD 0.7 VDD 0.8 VDD 0.8 VDD 0.8 VDD 0.8 VDD typ max 6.0 6.0 13.5 VDD VDD 13.5 Unit V V V V V V
VDD VDD VDD
V V V
Continued on next page.
No. 6498-21/39
LC651432N/F/L, 651431N/F/L
Continued from preceding page.
Parameter Symbol Conditions With the n-channel output transistors off VDD = 4 to 6 V With the n-channel output transistors off 3 to 6 V With the n-channel output transistors off VDD = 4 to 6 V With the n-channel output transistors off 3 to 6 V External clock specifications VDD = 4 to 6 V External clock specifications 3 to 6 V VDD = 4 to 6 V 3 to 6 V VDD = 4 to 6 V 3 to 6 V Applicable pins Ratings min VSS typ max 0.3 VDD Unit
VIL(1)
Port
V
VIL(2)
Port
VSS
0.25 VDD
V
VIL(3)
INT, SCK, SI
VSS
0.25 VDD
V
VIL(4) Low-level input voltage VIL(5) VIL(6) VIL(7) VIL(8) VIL(9) VIL(10) Operating frequency (cycle time) External clock conditions Frequency Pulse width Rise and fall time Recommended oscillator circuit constants Ceramic oscillator*4 text fop (Tcyc)
INT, SCK, SI
VSS
0.2 VDD
V
OSC1 OSC1 TEST TEST RES RES
VSS VSS VSS VSS VSS VSS 200 (20)
0.25 VDD 0.2 VDD 0.3 VDD 0.25 VDD 0.25 VDD 0.2 VDD 4330 (0.92)
V V V V V V kHz (s)
OSC1 OSC1 OSC1
200 69
4330
kHz ns
textH, textL See figure 1. textR, textF
50
ns
See figure 2.
See table 1.
No. 6498-22/39
LC651432N/F/L, 651431N/F/L Electrical Characteristics at Ta = -40 to +85C, VSS = 0 V, VDD = 3.0 to 6.0 V (unless otherwise specified)
Parameter Symbol Conditions * With the output n-channel transistors off (Including the n-channel transistor off leakage current.) * VIN = 13.5 V * With the output n-channel transistors off (Including the n-channel transistor off leakage current.) * VIN = VDD External clock mode VIN = VDD * With the output n-channel transistors off * VIN = VSS * With the output n-channel transistors off * VIN = VSS VIN = VSS External clock mode VIN = VSS * IOH = -50 A * IOH = -10 A * IOL = 10 mA IOL = 1 mA, when IOL for all ports is less than or equal to 1 mA. Applicable pins Open-drain specification ports (except I0) 5.0 A Ratings min typ max Unit
IIH(1)
High-level input current IIH(2)
The I0 port with open-drain specifications 1.0 A
IIH(3) IIL(1)
OSC1
1.0
A
Open-drain specification ports Built-in pull-up resistor specification ports RES OSC1 Built-in pull-up resistor specification ports Built-in pull-up resistor specification ports Ports Ports
-1.0
A
Low-level input current
IIL(2) IIL(3) IIL(4) VOH(1)
-1.3 -45 -1.0 VDD - 1.2 VDD - 0.5
-0.35 -10
mA A A V V 1.5 0.5 V V
High-level output voltage VOH(2) VOL(1) Low-level output voltage VOL(2) Schmitt characteristics
Hysteresis voltage
VHIS RES, INT, SCK, SI, and OSC1 with Schmitt trigger specifications*5
0.1 VDD
V
High-level threshold voltage
VtH
0.4 VDD
0.8 VDD
V
Low-level threshold voltage
VtL
0.2 VDD
0.6 VDD
V
Current drain*6 Ceramic oscillator External clock IDDOP(1) IDDOP(2) Standby mode IDDst * Figure 2, 4 MHz* * 200 to 4330 kHz* *: Operating, with the output n-channel transistors off, port voltage = VDD With the output n-channel transistors off, VDD = 6 V Port voltage = VDD, VDD = 3 V VDD VDD 1.5 4 mA
1
4
mA
VDD VDD
0.05 0.025
10 5
A A
Continued on next page.
No. 6498-23/39
LC651432N/F/L, 651431N/F/L
Continued from preceding page.
Parameter Oscillator characteristics Ceramic oscillator Oscillator frequency Oscillator stabilization time*8 fCFOSC tCFS RPP Ru External reset characteristics Reset time Pin capacitance Serial clock Input clock cycle time Output clock cycle time Input clock low-level pulse width Output clock low-level pulse width Input clock high-level pulse width Output clock high-level pulse width Serial input Data setup time Data hold time Serial output Output delay time tCKO * Stipulated with respect to the SCK falling edge. * With external 1 k resistors and 50 pF capacitors on the n-channel open-drain outputs only. * See figure 5 * See figure 6 * TCYC = 4 x * With external 1 k resistors and external 50 pF capacitors on the n-channel open-drain outputs only. tICK tCKI Stipulated with respect to the SCK rising edge. See figure 5. SI SI 0.5 0.5 s s tCKCY(1) tCKCY(2) tCKL(1) See figure 5. See figure 5. See figure 5. SCK SCK SCK SCK SCK SCK 1.0 32 x TCYC 1.0 32 x TCYC 2.0 64 x TCYC*9 s s s s s s tRST Cp * f = 1 MHz * With all pins except the pin being tested at VIN = VSS. * Figure 2, fo = 4 MHz*7 * Figure 3, fo = 4 MHz * Output n-channel transistors off * VIN = VSS, VDD = 5 V * VIN = VSS, VDD = 5 V Ports with built-in pull-up resistor specifications RES OSC1, OSC2 3920 4000 4080 10 kHz ms Symbol Conditions Applicable pins Ratings min typ max Unit
Built-in pull-up resistor I/O ports RES
8 200
14 500 See figure 4. 10
30 800
k k
pF
tCKL(2) tCKH(1) tCKH(2)
See figure 5. See figure 5. See figure 5.
SO
0.5
s
Pulse output Period High-level pulse width tPCY tPH PE0 PE0 64 x TCYC 32 x TCYC 10% 32 x TCYC 10% s s
Low-level pulse width
tPL
PE0
s
Notes: 1. Voltages up to the generated oscillation amplitude are allowed with internal drive using the oscillator circuit of figure 2 and the recommended circuit constants. 2. The average over a 100 ms period. 3. Applications must hold the operating supply voltage VDD level from the point a HALT instruction is executed until the IC enters the standby state. Also, switch bounce and similar noise must not appear on PA3 (or PA0 to 3) during the HALT instruction execution cycle. 4. The recommended circuit constants for which stable oscillation has been verified with the manufacturer of the oscillator element using the Sanyo specified oscillator characteristics evaluation board. 5. The OSC1 pin has Schmitt trigger characteristics when external clock is specified as the oscillator option. 6. The result of measurement when the recommended external circuit constants are used with the Sanyo characteristics evaluation board. The current due to the IC output transistors and pull-up resistor transistors is not included. 7. Indicates the frequency when fCFOSC is due to the use of the recommended circuit constants in table 1. 8. Indicates the required time for oscillation to stabilize starting from the point when VDD first exceeds the lower limit of the operating supply voltage range. (See figure 3.) 9. TCYC = 4 x
No. 6498-24/39
LC651432N/F/L, 651431N/F/L
OSC1
(OSC2)
External clock
Open
VDD 0.8 VDD
0.25 VDD VSS
text
text
text text
text
Figure 1 External Clock Input Waveform
OSC1
OSC2
R
C1 Ceramic oscillator element
C2
Figure 2 Ceramic Oscillator Circuit
No. 6498-25/39
LC651432N/F/L, 651431N/F/L
VDD
Lower limit of the operating VDD range 0V
OSC
Oscillator stabilization time tCFS
Stable oscillation
Figure 3 Oscillator Stabilization Time
Table 1 Ceramic Oscillator Recommended Circuit Constants
4 MHz (Murata Mfg. Co., Ltd.) CSA4.00MG CST4.00MGW (Built-in capacitor) 4 MHz (Kyocera Corporation) KBR4.0MSB KBR4.0MKC (Built-in capacitor) C1 C2 R C1 C2 R 33 pF 10% 33 pF 10% 0 33 pF 10% 33 pF 10% 0
RES CRES ( = 0.1 F)
Sanyo is currently requesting evaluation of oscillator element products and recommended circuit constants from Kyocera Corporation for their products, and thus these recommendations are subject to change. Contact your Sanyo representative before using these devices.
Figure 4 Reset Circuit
Note: When the power supply rise time is effectively zero, the reset time for a CRES of 0.1 F will be between 10 and 100 ms. If the power supply rise time is relatively long, increase the value of CRES so that the reset time is over 10 ms.
No. 6498-26/39
LC651432N/F/L, 651431N/F/L
tCKCY 0.8 VDD tCKL SCK tICK SI tCKO SO Output data 50 pF tCKI 1 k tCKH 0.25 VDD
VDD
Input data Load circuit
Figure 5 Serial I/O Timing
tPCY tPH 0.7 VDD tPL The load conditions are the same as those in figure 5. 0.3 VDD
Figure 6 Port PE0 Pulse Output Timing
No. 6498-27/39
LC651432N/F/L, 651431N/F/L
LC651432L, 651431L
Absolute Maximum Ratings at Ta = 25C, VSS = 0 V
Parameter Maximum supply voltage Output voltage Symbol VDD max VO VI(1) VI(2) VIO(1) I/O voltage VIO(2) VIO(3) Peak output current IOP IOA IOA(1) Per single pin, the average over a 100 ms period The total current for PC0 to 3, PD0 to 3, and PE0 to 3*2 The total current for PF0 to 3, PG0 to 3, PA0 to 3, and PI0*2 Conditions VDD OSC2 OSC1 *1 TEST, RES Ports with open-drain specifications Ports with pull-up resistor specifications PI0 I/O ports I/O ports PC0 to 3 PD0 to 3 PE0 to 3 PF0 to 3, PI0 PG0 to 3 PA0 to 3 Applicable pins Ratings -0.3 to +7.0 Voltages up to the voltage generated are allowed. -0.3 to VDD +0.3 -0.3 to VDD +0.3 -0.3 to +15 -0.3 to VDD +0.3 -0.3 to VDD +0.3 -2 to +20 -2 to +20 Unit V V V V V V V mA mA mA
Input voltage
Average output current
-15 to +100
IOA(2)
-15 to +100 310 220 160 -40 to +85 -55 to 125
mA mW mW mW C C
Pd max(1) Ta = -40 to +85C (DIP package) Allowable power dissipation Pd max(2) Ta = -40 to +85C (MFP package) Pd max(3) Ta = -40 to +85C (SSOP package) Operating temperature Storage temperature Topr Tstg
Allowable Operating Ranges at Ta = -40 to +85C, VSS = 0 V, VDD = 2.2 to 6.0 V (unless otherwise specified)
Parameter Operating supply voltage Standby supply voltage Symbol VDD VST VIH(1) VIH(2) VIH(3) High-level input voltage VIH(4) VIH(5) VIH(6) VIH(7) VIL(1) VIL(2) Low-level input voltage VIL(3) VIL(4) VIL(5) RAM and register contents retained. *2 With the n-channel output transistors off With the n-channel output transistors off With the n-channel output transistors off With the n-channel output transistors off With the n-channel output transistors off VDD = 1.8 to 6 V External clock specifications With the n-channel output transistors off With the n-channel output transistors off External clock specifications Conditions VDD VDD Ports with open-drain specifications (except for I0) Ports with pull-up resistor specifications (except for I0) Port I0 The INT, SCK, and SI pins with open-drain specifications The INT, SCK, and SI pins with pull-up resistor specifications RES OSC1 Ports INT, SCK, SI OSC1 TEST RES Applicable pins Ratings min 2.2 1.8 0.7 VDD 0.7 VDD 0.7 VDD 0.8 VDD 0.8 VDD 0.8 VDD 0.8 VDD VSS VSS VSS VSS VSS typ max 6.0 6.0 13.5 VDD VDD 13.5 Unit V V V V V V
VDD VDD VDD 0.2 VDD 0.2 VDD 0.15 VDD 0.22 VDD 0.15 VDD
V V V V V V V V
Continued on next page.
No. 6498-28/39
LC651432N/F/L, 651431N/F/L
Continued from preceding page.
Parameter Symbol Conditions When the built-in divide-byfour circuit is selected, the clock frequency upper limit is 4.16 MHz. Applicable pins Ratings min typ max Unit
Operating frequency (cycle time) External clock conditions Frequency Pulse width Rise and fall time Recommended oscillator circuit constants Two-pin RC oscillator Ceramic oscillator*4
fop (Tcyc)
200 (20)
1040 (3.84)
kHz (s)
Figure 1. If the clock frequency exceeds 1.040 MHz, either the divide-bytextH, textL three or the divide-by-four divider circuit option must be textR, textF selected. text
OSC1 OSC1 OSC1
200 120
4160
kHz ns
100
ns
Cext Rext
See figure 2. See figure 3.
OSC1, OSC2
220 5% 12 1% See table 1.
pF k
No. 6498-29/39
LC651432N/F/L, 651431N/F/L Electrical Characteristics at Ta = -40 to +85C, VSS = 0 V, VDD = 2.2 to 6.0 V (unless otherwise specified)
Parameter Symbol Conditions * With the output n-channel transistors off (Including the n-channel transistor off leakage current.) * VIN = 13.5 V * With the output n-channel transistors off (Including the n-channel transistor off leakage current.) * VIN = VDD External clock mode VIN = VDD * With the output n-channel transistors off * VIN = VSS * With the output n-channel transistors off * VIN = VSS VIN = VSS External clock mode VIN = VSS * IOH = -10 A * IOL = 3 mA IOL = 1 mA, when IOL for all ports is less than or equal to 1 mA. Applicable pins Open-drain specification ports (except I0) 5.0 A Ratings min typ max Unit
IIH(1)
High-level input current IIH(2)
The I0 port with open-drain specifications 1.0 A
IIH(3) IIL(1)
OSC1
1.0
A
Open-drain specification ports Built-in pull-up resistor specification ports RES OSC1 Built-in pull-up resistor Ports Ports
-1.0
A
Low-level input current
IIL(2) IIL(3) IIL(4)
-1.3 -45 -1.0 VDD - 0.5
-0.35 -10
mA A A V 1.5 0.4 V V
High-level output voltage
VOH VOL(1)
Low-level output voltage
VOL(2)
Schmitt characteristics
Hysteresis voltage
VHIS RES, INT, SCK, SI, and OSC1 with Schmitt trigger specifications*5
0.1 VDD
V
High-level threshold voltage
VtH
0.4 VDD
0.8 VDD
V
Low-level threshold voltage
VtL
0.2 VDD
0.6 VDD
V
Current drain*6 Two-pin RC oscillator IDDOP(1) * While operating, with the output n-channel transistors off * Port voltage = VDD * Figure 2, fosc = 400 kHz (typical) * Figure 3, 4 MHz, divideby-four circuit used. * Figure 3, 4 MHz, divideby-four circuit used. VDD = 2.2 V See figure 3. 400 kHz
VDD
0.8
2.5
mA
Ceramic oscillator External clock
IDDOP(2) IDDOP(3) IDDOP(4)
VDD VDD VDD
1 0.3
3 1
mA mA
Standby mode
1
2.5
mA
IDDOP(5)
* 200 to 1024 kHz, no divider * 600 to 3120 kHz, divideby-three circuit used VDD * 800 to 4160 kHz, divideby-four circuit used Output n-channel transistors off, VDD = 6 V Port voltage = VDD, VDD = 2.2 V VDD VDD
1.5
4
mA
0.05 0.025
10 5
A A
IDDst
Continued on next page.
No. 6498-30/39
LC651432N/F/L, 651431N/F/L
Continued from preceding page.
Parameter Oscillator characteristics Ceramic oscillator Oscillator frequency fCFOSC*7 * Figure 3, fo = 400 kHz * Figure 3, fo = 4 MHz, divide-by-four circuit used. * Figure 4, fo = 400 kHz * Figure 4, fo = 800 kHz, 1 MHz, or 4 MHz, divideby-four circuit used. * Figure 2, Cext = 220 pF 5% OSC1, OSC2 * Figure 2, Rext = 12 k 1% * Output n-channel transistors off * VIN = VSS, VDD = 5 V * VIN = VSS, VDD = 5 V Ports with built-in pull-up resistor specifications RES 200 400 OSC1, OSC2 OSC1, OSC2 392 3920 400 4000 408 4080 kHz kHz Symbol Conditions Applicable pins Ratings min typ max Unit
Oscillator stabilization time*8 tCFS Two-pin RC oscillator Oscillator frequency Built-in pull-up resistor I/O ports RES
10 10
ms ms
fMOSC RPP Ru
790
kHz
8 200
14 500 See figure 5.
30 800
k
External reset characteristics Reset time Pin capacitance Serial clock Input clock cycle time Output clock cycle time Input clock low-level pulse width Output clock low-level pulse width Input clock high-level pulse width Output clock high-level pulse width Serial input Data setup time Data hold time Serial output Output delay time
tRST Cp * f = 1 MHz * With all pins except the pin being tested at VIN = VSS. See figure 6. See figure 6. See figure 6. SCK SCK SCK SCK SCK SCK 4.0 4.0 12.0
10
pF
tCKCY(1) tCKCY(2) tCKL(1)
s 64 x TCYC*9 s s 32 x TCYC s s 32 x TCYC s
tCKL(2) tCKH(1) tCKH(2)
See figure 6. See figure 6. See figure 6.
tICK tCKI tCKO
Stipulated with respect to the SCK rising edge. See figure 6.
SI SI
0.5 0.5
s s
* Stipulated with respect to the SCK falling edge. * With external 1 k resistors and 50 pF capacitors on the n-channel open-drain outputs only. * See figure 6 * See figure 7
SO
2.0
s
Pulse output Period High-level pulse width tPCY tPH
* TCYC = 4 x * With external 1 k resistors and external 50 pF capacitors on the n-channel open-drain outputs only.
PE0 PE0
64 x TCYC 32 x TCYC 10% 32 x TCYC 10%
s s
Low-level pulse width
tPL
PE0
s
No. 6498-31/39
LC651432N/F/L, 651431N/F/L
Notes: 1. Voltages up to the generated oscillation amplitude are allowed with internal drive using the oscillator circuit of figure 3 and the recommended circuit constants. 2. The average over a 100 ms period. 3. Applications must hold the operating supply voltage VDD level from the point a HALT instruction is executed until the IC enters the standby state. Also, switch bounce and similar noise must not appear on PA3 (or PA0 to 3) during the HALT instruction execution cycle. 4. The recommended circuit constants for which stable oscillation has been verified with the manufacturer of the oscillator element using the Sanyo specified oscillator characteristics evaluation board. 5. The OSC1 pin has Schmitt trigger characteristics when either 2-pin RC oscillator or external clock input is specified as the oscillator option. 6. The result of measurement when the recommended external circuit constants are used with the Sanyo characteristics evaluation board. The current due to the IC output transistors and pull-up resistor transistors is not included. 7. Indicates the frequency when fCFOSC is due to the use of the recommended circuit constants in table 1. 8. Indicates the required time for oscillation to stabilize starting from the point when VDD first exceeds the lower limit of the operating supply voltage range. (See figure 4.) 9. TCYC = 4 x
No. 6498-32/39
LC651432N/F/L, 651431N/F/L
OSC1
(OSC2)
External clock
Open
VDD 0.8 VDD
0.15 VDD VSS
text
text
text text
text
Figure 1 External Clock Input Waveform
OSC1
OSC2
OSC1
OSC2
R Rext Cext C1 Ceramic oscillator element C2
Figure 2 Two-Pin RC Oscillator Circuit
Figure 3 Ceramic Oscillator Circuit
No. 6498-33/39
LC651432N/F/L, 651431N/F/L
VDD
Lower limit of the operating VDD range 0V
OSC
Oscillator stabilization time tCFS
Stable oscillation
Figure 4 Oscillator Stabilization Time
Table 1 Ceramic Oscillator Recommended Circuit Constants
4 MHz (Murata Mfg. Co., Ltd.) CSA4.00MGU CST4.00MGWU (Built-in capacitor) 400 kHz (Murata Mfg. Co., Ltd.) CSB400P C1 C2 R C1 C2 R 33 pF 10% 33 pF 10% 0 330 pF 10% 330 pF 10% 3.3 k
RES CRES ( = 0.1 F)
Figure 5 Reset Circuit
Note: When the power supply rise time is effectively zero, the reset time for a CRES of 0.1 F will be between 10 and 100 ms. If the power supply rise time is relatively long, increase the value of CRES so that the reset time is over 10 ms.
No. 6498-34/39
LC651432N/F/L, 651431N/F/L
tCKCY tCKL SCK tICK SI tCKO Output data 50 pF tCKI 1 k tCKH 0.8 VDD 0.2 VDD
VDD
Input data Load circuit
SO
Figure 6 Serial I/O Timing
tPCY tPH 0.7 VDD tPL The load conditions are the same as those in figure 6. 0.25 VDD
Figure 7 Port PE0 Pulse Output Timing
No. 6498-35/39
LC651432N/F/L, 651431N/F/L LC651431L and LC651432L RC Oscillator Characteristics Figure 8 shows the LC651431L and LC651432L RC oscillator characteristics. However, the LC651431L and LC651432L have the following RC oscillator frequency sample-to-sample variations. VDD = 2.2 to 6.0 V, Ta = -40 to 85C When the external circuit constants are: Cext = 220 pF, and Rext = 12 k, the frequency range will be: 200 kHz fMOSC 790 kHz Note that only the above circuit constants are guaranteed. If using other values for these constants is unavoidable, use values in the following ranges. Cext = 150 to 390 pF Rext = 3 to 20 k (See figure 8.)
Notes: 10. The oscillator frequency must be in the range 350 to 500 kHz when VDD = 5.0 V and Ta = 25C. 11. Applications must assure adequate margins so that oscillator frequency falls in the operating clock frequency range (in the oscillator divider option table) for the ranges VDD = 2.2 to 6.0 V and Ta = -40 to 85C.
f 1.5
MOSC-Rext
C = 150p
These characteristics curves are for reference purposes only. These characteristics are not guaranteed.
[kHz]
1000 9 8 7 6 5 4 3
C = 270p
f
MOSC
C = 390p
2
VDD = 5 (V) Ta = 25C 1000 3 4 5 1 Rext [k] 2 3 4 5 10
Figure 8 RC Oscillator Frequency Data (representative values)
No. 6498-36/39
LC651432N/F/L, 651431N/F/L Notes on PCB Construction This section presents notes on noise as seen from the microcontroller itself and methods for reducing such noise when designing the printed circuit board for a mass-produced product using these microcontrollers. The design techniques presented here can be effective for preventing or avoiding problems (such as microcontroller malfunction and program runaway) due to noise. 1. VDD and VSS: Power supply pins Insert capacitors that meet the following conditions between the VDD and VSS pins. * For each of the capacitors C1 and C2, make the wiring lengths from the IC as close to equal as possible (L1 = L1' and L2 = L2'), and keep these lines as short as possible as well. * Insert the capacitors C1, a large capacitor, and C2, a small capacitor, in parallel. * The VDD and VSS lines in the printed circuit board pattern should be wider than any other lines.
L2 L1 C1 + L1' L2' C2 VDD VSS
2. OSC1 and OSC2: Clock input and output pins When the ceramic oscillator option is selected (figure 2-1) * Keep the length (LOSC) of the connection lines between the clock I/O pins (input: OSC1, output: OSC2) and the external components as short as possible. * Keep the length (LVSS + L1 (L2)) from the VSS side of the capacitor connected to the oscillator element to the VSS pin as short as possible. * VSS line for the oscillator circuit and other VSS lines should branch from a point nearest to the VSS pin. * There are cases where the values of the oscillator circuit components (the capacitors C1 and C2, the limit resistor Rd, and other components) must be modified from the values recommended in this document to adjust the oscillator frequency. Consult with the oscillator element manufacturer when determining the component values.
LVSS L1 L2 C2 Rd LOSC LVSS Lc Cext VSS Rext C1
VSS OSC1 OSC2
Figure 2-1 Oscillator Circuit Example 1 (ceramic oscillator)
OSC1 OSC2
When the 2-pin RC oscillator option is selected (figure 2-2) LOSC * Keep the length (LOSC) of the connection lines between the clock I/O pins (input: OSC1, output: OSC2) and the Figure 2-2 Oscillator Circuit Example 2 external components (the capacitor Cext and the resistor (2-pin RC oscillator) Rext) as short as possible. * Keep the length (LVSS + Lc) from the VSS side of the capacitor connected to the oscillator element to the VSS pin as short as possible. * VSS line for the oscillator circuit and other VSS lines should branch from a point nearest to the VSS pin.
No. 6498-37/39
LC651432N/F/L, 651431N/F/L When the external oscillator option is selected (figure 2-3) * Keep the length (LOSC) of the line between the external oscillator and the IC clock input pin (OSC1) as short as possible. * Also keep the length (LOSC) of the lines between the external oscillator and the VDD and VSS used as short as possible. Other common points: * Keep signals that change rapidly and large-amplitude signals connected to medium-voltage handling ports as far away from the oscillator circuit as possible and do not allow such lines to cross lines related to clock signals.
LOS VSS External oscillator OSC1 PI0 VDD
Figure 2-3 Oscillator Circuit Example 3 (external oscillator)
3. RES: Reset pin * Keep the line from the external reset circuit to the RES pin as short as possible. * Keep the length (L1, L2) of the lines from the capacitor (Cres) inserted between RES and VSS as short as possible.
L2 External circuit Cres
VSS
RES L1 Lres
Figure 3 RES Pin Wiring 4. TEST: Test pin * Keep the line that connects the TEST pin to VSS as short as possible. * Take the line that connects the TEST pin to VSS from a location as close to the VSS pin as possible.
VSS L TEST
Figure 4 TEST Pin Wiring
No. 6498-38/39
LC651432N/F/L, 651431N/F/L 5. I/O pins All of the pins on these microcontrollers are shared-function I/O pins. * When used as input pins, insert limiting resistors and keep the connection lines as short as possible. Supplement: This can be effective in preventing or avoiding microcontroller problems (such as malfunctions and program runaway), not only in printed circuit board design, but in selecting the microcontroller option types discussed below and when considering application program specifications. * If signals are input when the microcontroller power supply is unstable, select the medium-voltage (n-channel open drain) output as the output circuit type for that pin, and also insert a limiting resistor as close to the pin as possible. * Always adopt key bounce elimination techniques when inputting external signals to any microcontroller pin. * Periodically refresh the pin output data with an output instruction (OP or SPB). * When reading data input to a shared-function (bidirectional) I/O pin, set the value of the output data for that pin to 1 on every read operation with an output instruction (OP or SPB). 6. Unused pins * Refer to the pin functions table in the user's manual for the product itself or in the relevant Sanyo Semiconductor Development Report. The information presented in this document consists of examples, and its use is not guaranteed in mass-produced end products. In actual product design (including the selection of circuit component values), we strongly recommend using the materials presented here as a reference and performing thorough evaluation and testing.
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of April, 2000. Specifications and information herein are subject to change without notice. PS No. 6498-39/39

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